Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), to name a few examples. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. Some FETs have a fourth terminal called, the body or substrate, which can be used to bias the transistor. A metal-oxide-semiconductor FET (MOSFET) is configured with an insulator between the gate and the body of the transistor, and MOSFETs are commonly used for amplifying or switching electronic signals. In some cases, MOSFETs include side-wall or so-called gate spacers on either side of the gate that can help determine the channel length and can help with replacement gate processes, for example. Complementary MOS (CMOS) structures typically use a combination of p-type MOSFETs (p-MOS) and n-type MOSFETs (n-MOS) to implement logic gates and other digital circuits.
A finFET is a transistor built around a thin strip of semiconductor material (generally referred to as a fin). The transistor includes the standard FET nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a finFET design is sometimes referred to as a tri-gate transistor. Tri-gate transistors are one example of non-planar transistor configurations, and other types of non-planar configurations are also available, such as so-called double-gate transistor configurations, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). Another non-planar transistor configuration is a gate-all-around configuration, which is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires (or nanoribbons) are used and the gate material generally surrounds each nanowire.
These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.